1. Technical Field
The present invention relates to a semiconductor circuit, and more particularly, to a column repair circuit.
2. Related Art
In general, a semiconductor memory apparatus includes a plurality of mats, and each mat includes numerous memory cells. A failure in any one of the numerous memory cells may cause the semiconductor memory apparatus to malfunction, which may lead to the entire semiconductor memory apparatus to be discarded as a defective product. Therefore, a repair circuit is used to replace the failed memory cell with a cell included in a redundancy circuit. When a failure occurs in a memory cell, the repair circuit recognizes the failed memory cell in advance, and when access to the corresponding memory cell is requested, the repair circuit replaces the memory cell with the cell included in the redundancy circuit. Here, the redundancy circuit refers to a group of spare memory cells which are separately prepared.
A variety of methods may be used to replace a failed memory cell with a redundancy memory cell. Such methods may include replacing a memory cell by row, replacing a memory cell by column, and replacing a memory cell by memory cell.
The method for replacing a memory cell by column corresponding to bit lines is generally used. In this method, when a failure occurs in a memory cell of a mat, a fuse is cut to replace a column including the failed memory cell with a redundancy column.
The above-described column repair method is advantageous in that a memory cell may be repaired using column addresses of the mat. However, when failures uniformly occur in memory cells of a plurality of mats, fuses of all corresponding mats must be cut. Furthermore, even when memory cell failures occur in portions of the mats, fuses of all corresponding mats must be cut. Thus, unnecessary repair time may be required, and excessive fuse cutting may reduce the reliability of the semiconductor apparatus.